Remember the sweetvar26 post about the PS4 chip?
Quote:
PS4:
New Starsha GNB 28nm TSMC
Milos
Southern Islands
DX11
SM 5.0
Open CL 1.0
Quad Pixel pipes 4
SIMD’s 5
Texture Units 5TCP/2TCC
Render back ends 2
Scalar ALU’s 320
EDIT: Some of those were crossed, may be they were updated/changed at a later date, I have no idea.
Quote:
Couple of more updates
Graphic North Bridge(GNB) Highlights
Fusion 1.9 support
DCE 7.0
UVD 4.0
VCE
IOMMU
ACP
5x8 GPP PCIE cores
SCLK 800MHz/LCLK 800MHz
Pretty weak compared to the PS4 GPU huh?
wait what the hell is a 'Graphic North Bridge'?
google & what do you find?
Rami Dornala - Graphic processor - Waltham, MA | Indeed
Quote:
Rami Dornala
Waltham, MA
Work Experience
Graphic processor
AMD - Waltham, MA
September 2011 to Present
Project:1 GNB core SOC
Duration: Sept 2011 , till date
Location: AMD
Description:
GNB core is based on the AMD fusion core technology, The GNB is a fusion of Graphic processor, power optimizer, audio processor, south bridge and north bridge which share a common interface with system memory.
Role: Tech Lead, Was responsible for Delivery of verification for Tapeout
Contribution:
1. Responsible for Functional verification of GNB.
2. Integrated ACP IP into the GNB environment
3. Integrated ISP IP into the GNB environment.
4. Aware of BIA, IFRIT flows.
5. Responsible for SAMARA and PENNAR integration.
6. Involved in kabini coverage closure, involved in LSC for kabini
7. Involved in fc mpu integration.
8. ONION and GARLIC bus OVC understanding and GNB environment set up for samara database.
9. Involved in LSA for Samara and Pennar GNB's
10. Involved in setting up of Pennar database with GF libraries
9.Involved with migration of Pennar database from TSMC to GF libraries.
Team Size: 12
Technology used:
Verification environment is a hybrid mixture of System-C, SystemVerilog and C++ language.GNB is targeted for 20nm technological library with GF foundaries.
Project:2 G4Main SOC
oh so it's a Graphic North Bridge yeah that make's sense! wait no it doesn't this is just as crazy as Mark Cerny saying that the PS4 custom chip is a south bridge.
Quote:
Realizing Energy Efficiency and Smoothness using a Second Custom Chip with Embedded CPU
Cerny: The second custom chip is essentially the Southbridge. However, this also has an embedded CPU. This will always be powered, and even when the PS4 is powered off, it is monitoring all IO systems. The embedded CPU and Southbridge manages download processes and all HDD access. Of course, even with the power off.
these people are crazy
wait what? ONION and GARLIC where have I seen that before?
As onQ123 pointed out, Cerny has said the chip in charge of background downloads and other basic OS functions are on the South Bridge... that makes sense as the ARM Trust Zone is part of the South Bridge as it has to keep the I/O secure...
So, if everything is in order. We have the custom South Bridge ARM chip and the CPU (Jaguar), GPU (7800 series GCN), and the custom GNB all in the AMD "Fusion" design for extremely efficient caching between the CPU and GPU.
TL;DR: (SOMEONE CORRECT ME IF I'M WRONG)
This provides a super fast and efficient way of caching data without having to do redundant work. Cerny mentioned CPU and GPU not having to copy redundant info from the cache in order to use it. It allow straight from CPU to GPU data transferring. All of this is integrated into the CPU, GPU and North Bridge (memory controller). All of this will significantly reduce latency beyond than just providing a large L2 cache because a lot of unnecessary work is cut out and more "shortcuts" are provided.
Even more TL;DR: Worried about GDDR5 latencies? Don't be. Large Cache, very capable bus, shortcuts and clever data transferring between CPU and GPU make that a non-issue.
Courtmeach Crushed!
Quote:
PS4:
New Starsha GNB 28nm TSMC
Milos
Southern Islands
DX11
SM 5.0
Open CL 1.0
Quad Pixel pipes 4
SIMD’s 5
Texture Units 5TCP/2TCC
Render back ends 2
Scalar ALU’s 320
EDIT: Some of those were crossed, may be they were updated/changed at a later date, I have no idea.
Quote:
Couple of more updates
Graphic North Bridge(GNB) Highlights
Fusion 1.9 support
DCE 7.0
UVD 4.0
VCE
IOMMU
ACP
5x8 GPP PCIE cores
SCLK 800MHz/LCLK 800MHz
Pretty weak compared to the PS4 GPU huh?
wait what the hell is a 'Graphic North Bridge'?
google & what do you find?
Rami Dornala - Graphic processor - Waltham, MA | Indeed
Quote:
Rami Dornala
Waltham, MA
Work Experience
Graphic processor
AMD - Waltham, MA
September 2011 to Present
Project:1 GNB core SOC
Duration: Sept 2011 , till date
Location: AMD
Description:
GNB core is based on the AMD fusion core technology, The GNB is a fusion of Graphic processor, power optimizer, audio processor, south bridge and north bridge which share a common interface with system memory.
Role: Tech Lead, Was responsible for Delivery of verification for Tapeout
Contribution:
1. Responsible for Functional verification of GNB.
2. Integrated ACP IP into the GNB environment
3. Integrated ISP IP into the GNB environment.
4. Aware of BIA, IFRIT flows.
5. Responsible for SAMARA and PENNAR integration.
6. Involved in kabini coverage closure, involved in LSC for kabini
7. Involved in fc mpu integration.
8. ONION and GARLIC bus OVC understanding and GNB environment set up for samara database.
9. Involved in LSA for Samara and Pennar GNB's
10. Involved in setting up of Pennar database with GF libraries
9.Involved with migration of Pennar database from TSMC to GF libraries.
Team Size: 12
Technology used:
Verification environment is a hybrid mixture of System-C, SystemVerilog and C++ language.GNB is targeted for 20nm technological library with GF foundaries.
Project:2 G4Main SOC
oh so it's a Graphic North Bridge yeah that make's sense! wait no it doesn't this is just as crazy as Mark Cerny saying that the PS4 custom chip is a south bridge.
Quote:
Realizing Energy Efficiency and Smoothness using a Second Custom Chip with Embedded CPU
Cerny: The second custom chip is essentially the Southbridge. However, this also has an embedded CPU. This will always be powered, and even when the PS4 is powered off, it is monitoring all IO systems. The embedded CPU and Southbridge manages download processes and all HDD access. Of course, even with the power off.
these people are crazy
wait what? ONION and GARLIC where have I seen that before?
As onQ123 pointed out, Cerny has said the chip in charge of background downloads and other basic OS functions are on the South Bridge... that makes sense as the ARM Trust Zone is part of the South Bridge as it has to keep the I/O secure...
So, if everything is in order. We have the custom South Bridge ARM chip and the CPU (Jaguar), GPU (7800 series GCN), and the custom GNB all in the AMD "Fusion" design for extremely efficient caching between the CPU and GPU.
TL;DR: (SOMEONE CORRECT ME IF I'M WRONG)
This provides a super fast and efficient way of caching data without having to do redundant work. Cerny mentioned CPU and GPU not having to copy redundant info from the cache in order to use it. It allow straight from CPU to GPU data transferring. All of this is integrated into the CPU, GPU and North Bridge (memory controller). All of this will significantly reduce latency beyond than just providing a large L2 cache because a lot of unnecessary work is cut out and more "shortcuts" are provided.
Even more TL;DR: Worried about GDDR5 latencies? Don't be. Large Cache, very capable bus, shortcuts and clever data transferring between CPU and GPU make that a non-issue.
Courtmeach Crushed!
so...........
